Semiconductor device performance improvements have historically been achieved by reducing device dimensions. The device miniaturization trend has progressed to a point where contemporary integrated circuits (ICs) are fabricated with deep sub-micron device feature sizes. The trend has placed increased emphasis on miniaturization of discrete passive components that are required to function with miniaturized active devices.
In addition to reduced feature sizes, recent trends have focused on replacing conventional aluminum with copper as the conductive medium. As wire widths in integrated circuits continue to shrink, the electrical conductivity of the wiring material itself becomes increasingly important. In this regard, aluminum, which has been the material of choice since the integrated circuit art began, is becoming less attractive than conductors such as gold, silver, and especially copper. Copper is also more resistant than aluminum to electromigration, a property that grows in importance as wire widths decrease. Electromigration is a mass transport effect caused by electrons in electrical current flow colliding with stationary atoms. The collision can push the stationary atoms in the direction of the electron flow. Effects of electromigration are most pronounced in narrow passages (i.e., areas of increased current density) and can lead to a contact void.
As a result of its numerous electrical advantages over aluminum, copper has found increased application in the creation of discrete components, most notably discrete capacitors that are formed within or above the surface of a semiconductor-based IC. Copper provides improved conductivity and reliability but does provide a process challenge where a layer of copper must be patterned and etched, partially due to the fact that copper does not readily form volatile species during the etching process. To overcome the etch problem, other methods of creating interconnect lines using copper have been proposed, including depositing copper patterns using selective electroless plating.
A limit on the speed of advanced ICs is set by a signal propagation delay in conductive interconnect lines, which is determined by the time constant of the lines. The time constant is the product of the resistance, R, of the line and the capacitance, C, between the line and all adjacent lines; hence, an RC time constant. Using a lower resistivity conductive material decreases interconnect RC time constant delays resulting in an overall increase in device speed.
Resistance, R, of a structure is determined by the following equation
  R  =            ρ      ⁢                          ⁢      L              W      ⁢                          ⁢      T      where ρ is the resistivity of a conductive material, L is the length of the conductive material, W is the width of the conductive material, and T is the thickness of the conductive material.
The limited availability of low-loss integrated capacitor structures has long hindered the development of integrated circuits such as passive filters, voltage controlled oscillators (VCO), matching networks, and transformers. Contemporary portable communications environments strive to achieve more fully integrated circuits that operate at radio frequencies (RF) and microwave frequencies. Recent trends indicate a push to integrate entire receivers onto a single substrate. Planar capacitors fabricated from high resistivity materials tend to suffer from high losses and low quality factors (Q factors) at radio frequencies. The losses and low Q factors are generally attributable to dielectric losses incurred from parasitic capacitances and resistive losses due to the use of thin conductors with relatively high resistance. The Q factor is defined as
      Q    =                  E        S                    E        1              ,where ES is energy that is stored in the reactive portion of the component and E1 is energy that is lost in the reactive portion of the component.
For high frequency signals, such as signals in the 10 GHz to 100 GHz range, the value of the Q factor obtained from silicon-based capacitors is significantly degraded. For applications in this high frequency range, monolithic capacitors have been researched using a base substrate other than silicon for the creation of the capacitors. Such monolithic capacitors have, for instance, been created using sapphire or GaAs as a base. These capacitors have a considerably lower parasitic capacitance than their silicon counterparts and therefore provide higher frequencies of resonance of an RC circuit. Where, however, more complex applications are required, the need still exists to create capacitors using silicon as a substrate base.
With reference to FIG. 1, a cross-sectional view of a prior art capacitor 100 forms a portion of an integrated circuit. A substrate 101 having a dielectric layer 103 is coated with thin layers of metal, such as a titanium (Ti)/titanium-nitride (TiN)/aluminum (Al)/TiN (i.e., Ti/TiN/Al/TiN) film stack. The thin layers of metal, after appropriate etching, serve as a bottom plate 105 of the capacitor 100. The bottom plate 105 is covered with a metal-insulator-metal (MIM) dielectric layer 107, followed by a capacitor top plate 109. The MIM dielectric layer 107 and top plate 109 may each be etched as shown. The top plate 109 is frequently comprised of either a Ti/TiN/Al/TiN metal film stack (i.e., the same type of metal film stack as the bottom plate 105) or may be comprised of Ti, tantalum (Ta), or tantalum nitride (TaN). Conductive lines (not shown) are provided to each of the capacitor plates 105, 109 by either additive or subtractive metal patterning processes.
In FIG. 2, an alternative prior art construction of an integrated circuit capacitor 200 includes a substrate 201, a copper-barrier layer 203, and portions of electroplated or sputtered first 205A and second 205B copper lines. In a typical damascene process, the copper-barrier layer 203 prevents migration of copper molecules into surrounding areas of the substrate 201. The copper-barrier layer 203 is formed from a material having high electrical conductivity while maintaining a low copper diffusivity to chemically isolate a copper conductor from the substrate 201. The copper-barrier layer 203 further provides for adhesion of the subsequently formed copper lines 205A, 205B. A blanket dielectric layer 207 is deposited over the substrate 201 and exposed portions of the first 205A and second 205B copper lines. A portion of the blanket dielectric layer 207 is etched to expose the second copper line 205B. The second copper line 205B forms the bottom plate of the integrated circuit capacitor 200. A Ta layer 209 is deposited followed by a MIM dielectric layer 211. A top plate 213 of the capacitor 200 is formed over the MIM dielectric layer 211. The top plate 213 is comprised of a Ti/TiN/Al/TiN metal film stack. Alternatively, the top plate 213 is comprised of Ti, Ta, or TaN. Conductive lines (not shown) are provided to each of the capacitor plates 205B, 213 by either additive or subtractive metal processes.
Either of the prior art alternatives described with reference to FIG. 1 or 2 have good linearity due to the planar design of each. The good linearity generally makes MIM planar capacitors a preferred choice in integrated circuit designs and specifically in radio-frequency applications.
However, the prior art alternatives also share similar limitations. RF applications also require a high Q factor. The Q factor, as shown above, is strongly dependent on the resistivity of the capacitor conducting plates. Since all of the materials listed in the prior art structures (e.g., Ti, TiN, Ta, Al, etc.) have a higher resistivity than copper, the Q factor will be low unless both conducting plates are fabricated from copper. Although some dual copper plate capacitor integrated circuit designs do exist, each is plagued by expensive damascene process steps required for each of the capacitor plates.
Therefore, what is needed is a dual copper plate integrated circuit capacitor and a process for producing the same which is readily and economically integrated into a typical fabrication process flow.